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INTEGRATED CIRCUITS
DATA SHEET
TDA1546T Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Preliminary specification File under Integrated Circuits, IC01 January 1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
CONTENTS 1 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 2 3 4 5 6 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.3.4 7.3.3.5 7.3.3.6 7.3.3.7 7.3.3.8 7.3.3.9 7.3.3.10 7.3.3.11 7.3.3.12 7.3.3.13 7.3.3.14 7.3.3.15 7.3.3.16 7.3.3.17 7.3.3.18 7.3.3.19 7.3.3.20 7.3.3.21 FEATURES Easy application High performance Digital sound processing features Volume control features Sound processing features Sound monitor features ORDERING INFORMATION QUICK REFERENCE DATA GENERAL DESCRIPTION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Clock generation and distribution Power-on reset Microprocessor interface Address mode Data transfer mode Organization and programming of the internal register file Volume control register bits: BAL3 to BAL0 and BAR3 to BAR0 Volume control register bits: VC7 to VC0 and FT3 to FT0 Volume control register bit: MUTE Volume control register bit: RUNFA Sound monitor register bits: FP2 to FP0 Sound monitor register bits: OVER3 to OVER0 Sound monitor register bits: SIL3 to SIL0 and SILT3 to SILT0 Sound monitor register bit SPOS Sound processing register bit: DSS Sound processing register bits: SCT3 to SCT0 Sound processing register bits: SCB3 to SCB0 Sound processing register bits: SCBB3 to SCBB0 Sound processing register bits: DEMC1 and DEMC0 Sound processing register bit: DSM Miscellaneous register bits: ED3 to ED0 Miscellaneous register bits: EA2 to EA0 Miscellaneous register bits: INS1 and INS0 Miscellaneous register bits: PVIV1, PVIV0 and PINM1, PINM0 Miscellaneous register bit: CLRM Miscellaneous register bits: OUTS1 and OUTS0 Miscellaneous register bit: LONLY 7.4 7.4.1 7.5 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.10 7.11 7.12 7.13 8 9 10 11 12 7.3.3.22
TDA1546T
Miscellaneous register bits: FSO1, FSO0, TRI, ACDT, DCDT, CLKIV, CLKON, DYC1 and DYC0 Multiple format input interface Synchronization Normal-speed mode Double-speed mode Double-speed mode features Low-power option using double-speed mode Volume control features Digital balance Digital volume control with fade function Digital soft-mute Scaling and polarity of the digital up-sampling filter Sound processing related features De-emphasis filter Treble Bass Bass boost Digital dynamic bass boost, digital loudness and other dynamic applications of tone control Digital speaker system mode Sound monitor block Spectrum analyzer dB converter Peak detection Silence detection Overload detection Versatile outputs Noise shaper Continuous calibration digital-to-analog converter Operational amplifiers Internal reference circuitry LIMITING VALUES THERMAL CHARACTERISTICS QUALITY SPECIFICATION CHARACTERISTICS ANALOG CHARACTERISTICS
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
13 13.1 13.2 14 15 15.1 15.1.1 15.1.2 15.1.3 16 17 18 APPLICATION INFORMATION Digital filter characteristics (theoretical values) Example application circuit PACKAGE OUTLINE SOLDERING Plastic small-outline packages By wave By solder paste reflow Repairing soldered joints (by hand-held soldering iron or pulse-heated solder tool) DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
TDA1546T
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
1 1.1 FEATURES Easy application 1.3.2 SOUND PROCESSING FEATURES
TDA1546T
* Voltage output 1.5 V (RMS) * Operational amplifiers and cascaded 4-stage digital FIR filter integrated * Master and slave mode clock system with selectable system clock (fsys) 256fs or 384fs * I2S-bus serial input format or Japanese 16, 18 or 20 bits serial input mode * All features are accessible under remote control * Simple 3-line serial microcontroller command interface * Power-on reset * 28 lead small outline package. 1.2 High performance
* Digital de-emphasis filter for three sample rates (32 kHz, 44.1 kHz or 48 kHz) * Digital treble: -10.5 dB to +12 dB at 20 kHz; 16 steps spaced at 1.5 dB * Digital bass: -9 dB to +13.5 dB at 20 Hz; 16 steps spaced at 1.5 dB * Distortion-free digital dynamic bass boost: 0 dB to +37 dB at 10 Hz; 15 steps spaced at 2 dB * Can be used for loudness or dynamic digital bass boost * Double-speed mode (e.g. for high-speed dubbing) * Pseudo double-speed mode (for power saving application) * Digital speaker system mode including digital crossover filter. 1.3.3 SOUND MONITOR FEATURES
* Superior signal-to-noise ratio * Low total harmonic distortion * Wide dynamic range * No zero crossing distortion * Continuous calibration digital-to-analog conversion combined with noise shaping techniques * Second-order noise shaper * 128 times oversampling in normal-speed mode * 64 times oversampling in double-speed mode. 1.3 1.3.1 Digital sound processing features VOLUME CONTROL FEATURES
* Spectrum analyzer for seven different frequency ranges * Digital silence detection. Level (-48 dB to dB, in steps of 3 dB) and duration (200 ms to 3.2 s, in steps of 200 ms at 44.1 kHz) programmable. Output via versatile pins. * Peak level detection and readout to microcontroller (dB linear, 0 dB to -90 dB in steps of 1.5 dB) * Digital overload detection. Level-programmable (dB linear, -1.5 dB to -46.5 dB, in steps of 3 dB). Output via versatile pins. * Digital spectrum analyzer by combination of peak detection and 7-band selective filter * Optional combination spectrum analyzer and overload detection for frequency-dependent overload detection.
* Smoothed transitions before and after digital mute (soft mute) * Fade function: duration-programmable (6 ms to 22.4 s at 44.1 kHz) digital volume control (attenuation as well as gain): +6 dB to -90 dB in steps of 0.375 dB with automatic soft mute * Digital balance: 0 dB to -22.5 dB in steps of -1.5 dB (maximum overall attenuation combined with volume control: -90 dB) 2 ORDERING INFORMATION TYPE NUMBER TDA1546T
PACKAGE NAME SO28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm VERSION SOT136-1
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
3 QUICK REFERENCE DATA SYMBOLS VDD IDDD IDDA IDDO IDDX VFS(rms) (THD+N)/S PARAMETER supply voltage digital supply current analog supply current operational amplifier supply current clock circuitry supply current full-scale output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio CONDITIONS note 1 note 2 note 2 note 2 note 2 VDD = 5 V at 0 dB signal level at -60 dB signal level; A-weighted S/N tdg BR signal-to-noise ratio at bipolar zero group delay A-weighted; at code 00000H fs = sample rate; normal-speed fs = 48 kHz; normal-speed fs = 48 kHz; double-speed fsys TCFS system clock frequency full-scale temperature coefficient at analog outputs (VOL and VOR) operating ambient temperature - - - - 1.425 - - - 100 - - - 6.4 - MIN. 3.8 5.0 40 5.5 6.5 1 1.5 -88 0.004 -44 108 24 ----fs - - - 100 x 10-6 TYP. - - - -
TDA1546T
MAX. 5.5 V
UNIT mA mA mA mA V dB % dB dB s Ms-1 Ms-1 MHz
1.575 -81 0.009 -40 - - 3.072 6.144 18.432 -
input bit rate at data input
Tamb Notes
-20
-
+70
C
1. All VDD and VSS pins must be connected to the same supply or ground respectively. 2. Measured at input code 00000H and VDD = 5 V.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
4 GENERAL DESCRIPTION
TDA1546T
The TDA1546T is the first Bitstream Continuous Calibration digital-to-analog converter (BCC-DAC) to feature unique signal processing functions. In addition to the basic functions of digital filtering and digital-to-analog conversion, it offers such advanced digital signal processing functions as volume control, tone control, bass boost, peak or spectrum analyzer readout and many more convenient functions. The digital processing features are of high sound quality due to the wide dynamic range of the bitstream conversion technique. The TDA1546T accepts I2S-bus data input formats with word lengths of up to 20 bits and various Japanese serial data input formats with word lengths of 16, 18 and 20 bits. The circuit can operate as a master or slave with different system clocks (256fs or 384fs) and is therefore, eminently suitable for use in various applications such as DCC, CD, DAT and MD.
The range of applications is further extended by an incorporated Digital Speaker System mode (DSS) with digital crossover filter. Four cascaded FIR filters and a sample-and-hold function increase the oversampling rate from 1fs to 96fs (384fs system clock) or 128fs (256fs system clock). A second-order noise shaper converts this oversampled data to a bitstream for the 5-bit DACs. The DACs are of the continuous calibration type and incorporate a special data coding technique, which contributes to a high signal-to-noise ratio and dynamic range. On-board amplifiers convert the output current to a voltage signal capable of driving a line output. Externally connected capacitors perform the required first-order filtering. Additional post filtering is not required.
Fig.1 Digital audio reconstruction system using the TDA1546T.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
5 BLOCK DIAGRAM
TDA1546T
handbook, full pagewidth
BCK 4
WS 5
DATA 6 MULTIPLE FORMAT INPUT INTERFACE
CKSL 7 12 CRYSTAL OSCILLATOR 13 16 XTAL1 XTAL2 CDEC
DE-EMPHASIS 14 15
SPECTRUM ANALYSER
VOLUME CONTROL BALANCE SOFT MUTE
VDDX VSSX
dB CONVERTER
PEAK DETECTION SILENCE DETECTION OVERLOAD DETECTION 21 VERS1 VERS0 20 VERSATILE OUTPUT SOURCE SELECTION
TONE CONTROL 1 BASS TONE CONTROL 2 TREBLE TONE CONTROL 3 BASS BOOST FIR FILTER STAGE 1:1f s to 2f s FIR FILTER STAGE 2:2f s to 4f s FIR FILTER STAGE 3:4f s to 8f s
CLOCK GENERATION AND DISTRIBUTION
10 9
VDDD VSSD
3 TEST1 11 TEST2
8 19 MICROCONTROLLER INTERFACE 18 17
TDA1546T
POR L3DATA L3CLK L3MODE
LINEAR INTERPOLATOR 8fs to 16fs 6 x OVERSAMPLING (SAMPLE-AND-HOLD) SECOND ORDER NOISE SHAPER DATA ENCODER LEFT OUTPUT SWITCHES
LINEAR INTERPOLATOR 8fs to 16fs 6 x OVERSAMPLING (SAMPLE-AND-HOLD) SECOND ORDER NOISE SHAPER DATA ENCODER RIGHT OUTPUT SWITCHES
FILTCL 23 R CONV1 1 nF CEXT1 VOL 22 2.2 k OP1
16 (4-bit) CALIBRATED CURRENT SOURCES
16 (4-bit) CALIBRATED CURRENT SOURCES
24 FILTCR R CONV2 2.2 k OP1 1 nF CEXT2 25 VOR
Vref 26 1 F GND 27 VSSO
16 (4-bit) CALIBRATED CURRENT SINKS
16 (4-bit) CALIBRATED CURRENT SINKS
REFERENCE SOURCE 28 VDDO 1 VDDA 2
MLC782
VSSA
Fig.2 Block diagram.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
6 PINNING DESCRIPTION Analog supply voltage Analog ground Test input 1. This pin should be connected to ground. Bit clock input Word select input Data input System clock frequency selection input Power-on reset (active LOW). Internal pull-up resistor allows timed operation in combination with external capacitor. Digital ground Digital supply voltage Test input 2. This pin should be connected to ground. Crystal oscillator input in master mode or external clock input in slave mode Crystal oscillator drive output to crystal Crystal oscillator supply voltage Crystal oscillator ground System clock output Identification of the L3-bus operation mode Bit clock for synchronization of microcontroller data transfer Bidirectional data line intended for control data from the microcontroller and peak data from the TDA1546T Versatile output 0 for silence or overload detection. Can be used to drive an LED. Versatile output 1 for silence or overload detection. Can be used to drive an LED. Left channel audio voltage output Capacitor for left channel first-order filter function should be connected between this pin and VOL (pin 22). VSSO VDDO 27 28 VOR Vref 25 26 SYMBOL PIN FILTCR 24
TDA1546T
SYMBOL PIN VDDA VSSA TEST1 BCK WS DATA CKSL POR 1 2 3 4 5 6 7 8
DESCRIPTION Capacitor for right channel first-order filter function should be connected between this pin and VOR (pin 25). Right channel audio voltage output Decoupling pin for internal reference voltage, 12VDDA (typ) Internal operational amplifier ground Internal operational amplifier supply voltage
VSSD VDDD TEST2 XTAL1 XTAL2 VDDX VSSX CDEC L3MODE L3CLK L3DATA
9 10 11 12 13 14 15 16 17 18 19
VERS0
20
VERS1
21
VOL FILTCL
22 23
Fig.3 Pin configuration.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7 FUNCTIONAL DESCRIPTION 7.1
TDA1546T
Clock generation and distribution
The TDA1546T CMOS digital-to-analog bitstream converter incorporates an up-sampling digital filter and noise shaper which increase the oversample rate of 1fs input data to 128fs in the normal-speed mode. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple first-order analog post-filtering. In the double-speed mode, the input sample frequency is twice that of the normal-speed mode, as is the signal bandwidth. The TDA1546T is able to distinguish between the two modes (by means of a special programming bit), so that in the double-speed mode, only half the amount of oversampling is applied, and digital filtering is applied over double the bandwidth compared to normal-speed. Thus in the double-speed mode, the input sample rate of 1fs input data is up-sampled by a factor 64fs, achieving the same absolute output sample frequency as in normal-speed mode. In the block diagram, Fig.2, a general subdivision into main functional Sections is illustrated. The actual signal processing takes place in the digital signal processing block. The two blocks named microcontroller interface and clock generation and distribution fulfil a general auxiliary function to the audio data processing path. The microcontroller interface provides access to all the blocks that require, or allow, configuration or selection and processes the data readout from the peak detection block, all via a simple three-line interface. The clock generation and distribution section, which is driven by the external system clock or crystal oscillator, provides the data processing blocks with time bases and controls the system mode dependent frequency settings. The following sections give detailed explanations of the operation of each block and their setting options processed by the microcontroller interface, the use of the microcontroller interface and of the operation of the clock section with its various system settings.
The TDA1546T has an internal clock generator that may be used by connecting a crystal of 11.2896 MHz (256fs) or 16.9344 MHz (384fs) between pins XTAL1 and XTAL2. This mode is used when the TDA1546T is the master in the system. The circuit diagram of Fig.4 shows the typical connection of the external oscillator circuitry for master mode operation. Alternatively, the TDA1546T can also operate in slave mode. Figure 5 shows how to connect for slave mode operation. In this mode, pin XTAL1 receives an input clock of 256 or 384fs (fs = 32, 44.1 or 48 kHz) and voltage levels of 0 V to 5 V by AC coupling and attenuation. The CDEC output (pin 16) contains a buffered version of the system clock for external use. The clock selection pin CKSL is used to select between system clock frequency ratios. Its effect is shown in Table 1. Table 1 System clock selection SYSTEM CLOCK 256fs 384fs CDEC OUTPUT 256fs 384fs
PIN CKSL 0 1
Fig.4 External crystal oscillator circuit.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7.3 Microprocessor interface
TDA1546T
The exchange of data and control information between the TDA1546T and a microcontroller is accomplished through a serial hardware interface comprising the following pins: L3DATA: microcontroller interface bidirectional data line. L3CLK: microcontroller interface clock line. L3MODE microcontroller interface mode line. Information transfer through the microcontroller bus is organized according to the so-called `L3' format, in which two different modes of operation can be distinguished; address mode and data transfer mode. The address mode is required to select a device communicating via the L3-bus and to determine the direction of data transfer in data transfer mode. Data transfer for the TDA1546T can be in two directions, input to the TDA1546T to program its sound processing and other functional features, and output from the TDA1546T for transfer of audio peak data, which it has acquired and processed, to the system microcontroller. 7.3.1 ADDRESS MODE
Fig.5 External clock input connection.
7.2
Power-on reset
The internal register file of the TDA1546T is initialized by a power-on reset sequence which can be instigated via the POR input pin 8. A LOW input on POR causes the reset sequence to be active. This input has an internal resistance to VDD to allow for passive use with only an external capacitor connected between this pin and ground. For correct detection by the TDA1546T internal controller, the system clock must be running, and POR should remain LOW for at least one audio sample period before being returned HIGH. Following detection another audio sample period is needed to complete the initialization procedure, after which the values of the various control bits in the internal register file are at their predefined initial values (see Section 7.3).
The address mode is used to select a device for subsequent data transfer and to define the direction of that transfer as well as the source or destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 clock pulses on L3CLK, accompanied by 8 data bits. The fundamental timing is shown in Fig.6.
Fig.6 Timing address mode.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Data bits 0 to 1 indicate the type of the subsequent data transfer as shown below in Table 2. The direction of the channel status and user data transfers depends on the transmit/receive mode. Table 2 BIT 1(1) X X Note 1. Where X = don't care. Data bits 2 to 7 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the Selection of data exchange BIT 0 0 1 TRANSFER data to TDA1546T data from TDA1546T DIRECTION input output
TDA1546T
TDA1546T is 000100 (bit 7 to bit 2). In the event that the TDA1546T receives a different address, it immediately 3-states the L3DATA pin and deselects its microcontroller interface logic. A dummy address of 000000 is defined for the deselection of all devices that are connected to the serial microcontroller bus. 7.3.2 DATA TRANSFER MODE
The selection performed in the address mode remains active during subsequent data transfers, until the TDA1546T receives a new address command. The fundamental timing of data transfers is shown in Fig.7, where L3DATA denotes the data from the TDA1546T to the microcontroller (L3DATA write). The timing for the opposite direction is essentially the same as in the address mode (L3DATA read). The maximum input clock and data rate is 64fs (or 32fs when in the double-speed mode).
Fig.7 Timing for data transfer mode.
All transfers are bytewise, i.e. they are based on groups of 8 bits. Data will be stored in the TDA1546T after the eighth bit of a byte has been received. A multi-byte transfer is illustrated in Fig.8. The definition of the L3 protocol allows for a so-called "halt" mode, as some devices which are expected to connect to the same microcontroller bus lines may require an indication of when
8 bits have been transferred. This halt mode option is implemented in the TDA1546T, meaning that subsequent byte transfers must be separated by a period identified as halt mode. A halt mode period is characterized by the following conditions: L3MODE = LOW, L3DATA = 3-state and L3CLK = HIGH.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
TDA1546T
Fig.8 Multibyte transfer.
7.3.3
ORGANIZATION AND PROGRAMMING OF THE
INTERNAL REGISTER FILE
Command data received from the microcontroller is stored in an internal register file (see Table 3) which is organized as a page of 16 registers, each containing a 4-bit command data word (D3 to D0). Table 3 Microcontroller control register file ADDRESS D3 A3 0 A2 0 A1 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BAL3 BAR3 VC3 VC7 FT3 DSS OVER3 SIL3 SILT3 MUTE SCT3 SCB3 SCBB3 FSO1 ED3 RUNFA BAL2 BAR2 VC2 VC6 FT2 FP2 OVER2 SIL2 SILT2 OUTS1 SCT2 SCB2 SCBB2 FSO0 ED2 EA2 BAL1 BAR1 VC1 VC5 FT1 FP1 OVER1 SIL1 SILT1 OUTS0 SCT1 SCB1 SCBB1 DEMC1 ED1 EA1 D2 D1
Access to the words in the register file involves selection of the address of a register location (by means of A3, A2, A1 and A0). A second page of 4 registers is accessible by means of the extended address register bits (EA2, EA1 and EA0) and extended data register bits (ED3, ED2, ED1 and ED0).
D0 BAL0 BAR0 VC0 VC4 FT0 FP0 OVER0 SIL0 SILT0 SPOS SCT0 SCB0 SCBB0 DEMC0 ED0 EA0
INITIAL STATE 1111 1111 1111 1110 0000 0000 1111 0000 0000 0000 0111 0110 0000 0000 1111 1111 balance left balance right
USED FOR
volume control volume control fade time digital speaker system; 3 x band-pass overload silence level silence time mute; 2 x output scaling; peak source treble bass bass boost 2 x reserved; 2 x de-emphasis extended data run fade; extended address
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Table 4 Extended microcontroller control register file INITIAL STATE 0000 0010 0011 0000
TDA1546T
EXTENDED ADDRESS EA2 0 0 0 0 EA1 0 0 1 1 EA0 0 1 0 1
ED3 INS1 PVIV1 CLKIV
ED2 INS0 PVIV0
ED1 DSM
ED0 CLRM
USED FOR input format; double-speed mode; clear memory polarity and function versatile output pins left only; 3 x reserved 4 x reserved
PINM1 PINM0 ACDT DCDT DYC0
LONLY TRI
CLKON DYC1
The following programming values for the various control words in the register file are given below.
7.3.3.7
Sound monitor register bits: SIL3 to SIL0 and SILT3 to SILT0
7.3.3.1
Volume control register bits: BAL3 to BAL0 and BAR3 to BAR0
Balance: a 4-bit value to program left channel attenuation (BAL3 to BAL0) and a 4-bit value to program right channel attenuation (BAR3 to BAR0). The range is 0 dB to -22.5 dB in steps of 1.5 dB (see Section 7.7.1).
Digital silence set numbers: a 4-bit value to program digital silence detection level -48 dB to dB (SIL3 to SIL0) and a 4-bit value to program digital silence duration 0.2 s to 3.2 s (SILT3 to SILT0) (see Section 7.9.4).
7.3.3.8
Sound monitor register bit SPOS
7.3.3.2
Volume control register bits: VC7 to VC0 and FT3 to FT0
Volume control set number: an 8-bit value to program volume control coefficient set (6 dB to -90 dB, in steps of 0.375 dB, VC7 to VC0); a 4-bit value to program fade time (6 ms to 22.4 s, FT3 to FT0) (see Section 7.7.2).
This bit controls the position of the spectrum analyzer. When SPOS = 1 the position of spectrum analyzer precedes the tone control sections. When SPOS = 0 the position of the spectrum analyzer succeeds the tone control sections.
7.3.3.9
Sound processing register bit: DSS
7.3.3.3
Volume control register bit: MUTE
Digital speaker system programming bit (see Section 7.8.6).
Digital soft mute control bit: logic 1 to activate mute and logic 0 to deactivate (see Section 7.7.3).
7.3.3.10
Sound processing register bits: SCT3 to SCT0
7.3.3.4
Volume control register bit: RUNFA
Treble coefficient set number: a 4-bit value to program digital treble coefficient set (see Section 7.8.2).
Function control bit: logic 1 to activate the volume control (after new fade time and/or volume control setting) (see Section 7.7.2.).
7.3.3.11
Sound processing register bits: SCB3 to SCB0
Bass coefficient set number: a 4-bit value to program digital bass coefficient set (see Section 7.8.3).
7.3.3.5
Sound monitor register bits: FP2 to FP0
7.3.3.12
Frequency range control bits (see Section 7.9.1).
Sound processing register bits: SCBB3 to SCBB0
7.3.3.6
Sound monitor register bits: OVER3 to OVER0
Overload detection level (dB linear; 0 dB to -45 dB, in steps of -3 dB) (see Section 7.9.5).
Bass boost coefficient set number: a 4-bit value to program digital bass boost coefficient set (see Section 7.8.4). This is also used for digital speaker system configuration (see Section 7.8.6).
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7.3.3.13 Sound processing register bits: DEMC1 and DEMC0
7.4
TDA1546T
Multiple format input interface
De-emphasis function enable and fs selection bits (see Section 7.8.1).
7.3.3.14
Sound processing register bit: DSM
Double-speed mode control bit: logic 1 to activate double-speed mode, logic 0 to deactivate (see Section 7.6).
7.3.3.15
Miscellaneous register bits: ED3 to ED0
Data input to the TDA1546T is accepted in four possible formats, I2S-bus (with word lengths of up to 20 bits), and LSB fixed formats of word lengths 16, 18 and 20 bits. As the resolution of the TDA1546T is 18 bits, input beyond this number does not affect the audio data processing. The general appearance of the permitted formats is given in Fig.9. The selection of a format is achieved through programming of the appropriate bits in the microcontroller register file. The truth table for these bits, INS1 and INS0, is given in Table 5. Characteristic timing for the input interface is given in the diagram of Fig.9. Table 5 Input format programming INS0 0 1 0 1 DATA INPUT FORMAT I2S-bus format LSB-justified format, 16 bits LSB-justified format, 18 bits LSB-justified format, 20 bits
Extended microcontroller control data (see Table 4).
7.3.3.16
Miscellaneous register bits: EA2 to EA0
INS1 0 0 1 1 7.4.1
Extended microcontroller register address (see Table 4).
7.3.3.17
Miscellaneous register bits: INS1 and INS0
Input format selection control bits (see Section 7.4).
7.3.3.18
Miscellaneous register bits: PVIV1, PVIV0 and PINM1, PINM0
SYNCHRONIZATION
These bits control the polarity (PVIV1 and PVIV0) and the output mode (PINM1 and PINM0) of the versatile output pins VERS1 and VERS0 (see Section 7.9.6).
7.3.3.19
Miscellaneous register bit: CLRM
Clear memory register bit: logic 1 to clear entire filter delay line (approximately 2 audio samples).
7.3.3.20
Miscellaneous register bits: OUTS1 and OUTS0
Output scaling factor control bits (see Table 10).
7.3.3.21
Miscellaneous register bit: LONLY
For correct data input to reach the central controller of the TDA1546T, synchronization must be achieved on the incoming 1fs I2S-bus or LSB justified format input signals. The incoming WS signal is sampled to detect whether its phase transitions belonging to left channel input occur at the correct synchronous timing instants. This sampling occurs at the TDA1546T internal clock rate. A correct phase transition of WS is expected after a fixed delay time of a previous correct transition, if not, the input will be regarded as out-of-lock. When such a condition occurs, the internal controller is instructed to wait for a period of 16 system clock cycles during which the expected WS transition must occur to achieve synchronization. The wait action is repeated as often as necessary until synchronization is achieved. To allow for slight disturbances, which would otherwise cause unnecessarily frequent resets, the critical WS transitions are expected within a tolerance window (rather than at one particular timing instant) of 32 system clock cycles. The phase, however, may vary according to the instant upon which synchronization has been achieved. The word select phase transition marking the start of right channel input data is expected after a fixed delay of the left channel synchronized WS transition, meaning that the input WS signal should be symmetrical in time (50% duty cycle measured in units of system clock cycles).
"Left Only" programming bit for use with digital speaker system mode (see Section 7.8.6).
7.3.3.22
Miscellaneous register bits: FSO1, FSO0, TRI, ACDT, DCDT, CLKIV, CLKON, DYC1 and DYC0
Register bits reserved for future use.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC) TDA1546T
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Fig.9 Input formats.
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
TDA1546T
Fig.10 Timing of input signals.
7.5
Normal-speed mode
7.6
Double-speed mode
In the normal-speed mode the oversampling filter consists of: * A 75th-order half-band low-pass FIR filter which increases the oversampling rate from 1 time to 2 times. * An 11th-order half-band low-pass FIR filter which increases the oversampling rate from 2 times to 4 times. * An 7th-order half-band low-pass FIR filter which increases the oversampling rate from 4 times to 8 times. * A linear interpolation section which increases the oversampling rate to 16 times. This removes the spectral components around 8fs. * A sample-and-hold section which provides another 6 times oversampling to 96 times. The zero-order hold characteristic of this sample-and-hold section plus the first-order analog filtering remove the spectral components around 16fs.
The double-speed is controlled by the register control bit DSM. When this bit is active HIGH the device operates in the double-speed mode. In the double-speed mode the oversampling filter consists of: * A 51st-order half-band low-pass FIR filter which increases the oversampling rate from 1 time to 2 times. * A 7th-order half-band low-pass FIR filter which increases the oversampling rate from 2 times to 4 times. * A linear interpolation section which increases the oversampling rate to 8 times. This removes the spectral components around 4fs. * A sample-and-hold section which provides another 6 times oversampling to 48 times. The zero-order hold characteristic of this sample-and-hold section plus the first-order analog filtering removes the spectral components around 8fs.
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7.6.1 DOUBLE-SPEED MODE FEATURES
TDA1546T
In the normal-speed mode all of the sound processing features such as those listed in the "Features" are available. However, the use of double-speed mode cuts down on the number of options due to the fact that a smaller cycle budget is available to the internal feature controller. Table 6 gives the availability of the different features in the double-speed mode. Table 6 Feature status in double-speed mode AVAILABLE yes yes no no no no yes no no yes yes yes yes although no detection takes place these pins respond to polarity setting fixed to before adapted scale: range from -96 dB to 0 dB volume change will be instantaneous fixed to flat response REMARKS
normal-speed. The same feature restrictions as in the double-speed mode apply, as does the filter performance specified for double-speed mode. The current consumption of the digital supply voltage is halved because of the lower absolute clock speed. In terms of conversion accuracy of the digital-to-analog converter section, some performance will however be sacrificed. 7.7 Volume control features
FEATURE Balance Volume Fade Band-pass filter Overload detection Silence detection Mute Peak position Treble, Bass Bass boost De-emphasis Clear memory Versatile pins
Features related to volume control are the digital balance control, digital volume control with fade function and the digital soft-mute. Their operation is described below. 7.7.1 Table 7 DIGITAL BALANCE Digital balance LEVEL (dB) 0 -1.5 ... -21.0 -22.5
BAL3 TO BAL0 BAR3 TO BAR0 1111 1110 .... 0001 0000
The balance value from 1111 to 0000 can be obtained using the following equation; Balance = -1.5 dB x (15 - balance setting) At extremely low volume settings (see Section 7.7.2) the range of effect of the balance control will be limited. The balance control effect will not go beyond an overall attenuation of 89.55 dB (balance plus volume control). 7.7.2 DIGITAL VOLUME CONTROL WITH FADE FUNCTION
Peak readout
yes
Because of the shift in scale of the volume control between normal and double-speed mode, a step in volume of 6 dB on switchover in either way should be compensated for by adjusting the volume during a preferably muted transition period. 7.6.2 LOW-POWER OPTION USING DOUBLE-SPEED MODE
The double-speed mode feature can also be used to cut down on power requirements. When the TDA1546T is switched to the double-speed mode using control bit DSM, and the system clock frequency is halved simultaneously, the filters will operate correctly on data input at January 1995 17
One of the features of the TDA1546T is an advanced digital volume control with inherent fading function. Only the desired volume and the fade speed need to be instructed to the TDA1546T, via the microcontroller interface. The single-bit flag RUNFA can then be used to inhibit or execute the volume change operation. When RUNFA = 0, the volume control settings can be changed without effect on the output. When RUNFA is then set to 1, the TDA1546T autonomously performs an automatic fade-in or fade-out to the desired volume by a natural, exponential approach. It allows for volume control to an accuracy of 0.375 dB from a gain of 6 dB of full-scale to -90 dB in normal-speed, and a range of 0 dB of full-scale to -96 dB in double-speed mode (see Tables 8 and 9).
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
In normal-speed operation the fade time can be set over a wide range, varying from 6 ms to over 20 seconds for a complete fade. The fade time is completely determined by the fade time setting and is independent of the amount of volume change programmed. This means that a smaller volume step will take the same amount of time but using a less steep slope than a larger volume change with the same fade time setting. In the double-speed mode the fade option is not available. Regardless of the current fade speed setting, a volume change in double-speed mode will take effect immediately, i.e. the next audio sample instant. Volume control data is in 2 nibbles and can be set in 256 steps. The relationship between command and output is shown in Tables 8 and 9. Table 8 Volume control VOLUME LEVEL VC7 TO VC0 1111 1111 1111 1110 .... 1111 0000 1110 1111 .... 0000 0001 0000 0000 Table 9 Fade control FT (DEC) 0 1 2 ... 14 15 FADE TIME AT 44.1 kHz (s) 0.006 0.2 0.6 .... 19.6 22.4 VC (DEC) NS 255 254 ... 240 239 ... 1 0 6.02 5.64 .... 0.37 0.00 .... -89.55 - DS 0 -0.37 .... -5.64 -6.02 .... -95.57 -
TDA1546T
The gain value ranging from 1111 1111 to 0000 000 can be converted to its logarithmic counterpart by the following equations: Normal-speed mode: 5 x ( log 2 ) G = ( volume setting - 239 ) x ---------------------------4 Example: attenuate data for 1111 11110: 5 x log 2 A = ( 254 - 239 ) x --------------------- = 5.64 dB 4 Double speed mode: 5 x ( log 2 ) G = ( volume setting - 255 ) x ---------------------------4 Example: attenuate data for 1111 11110: 5 x log 2 A = ( 254 - 255 ) x --------------------- = - 0.37 dB 4 The fade time from 0000 to 1111 can be converted by using the following equation: [ ( FT + 1 ) x ( FT x 16 + 1 ) ] x 256 Fade time = ------------------------------------------------------------------------------------------ fs Example: fade time for 0010 at fs = 44.1 kHz; fade time = 3 x 33 x 256/44100 = 0.57 s In Fig.11, a few fading examples illustrate the operation of the TDA1546T advanced digital volume control.
FT3 TO FT0 0000 0001 0010 .... 1110 1111
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Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
TDA1546T
(1) A = fade-out to zero volume (VC = 0; RUNFA = 1). (2) B = fade-in to maximum volume (RUNFA = 0; VC = 256; RUNFA = 1). (3) C = volume decrease (RUNFA = 0; VC = XXX; RUNFA = 1). (4) D = volume regulation override by resetting RUNFA to 0. (5) E = volume regulation resumed by resetting RUNFA to 1. (6) F = volume regulation stops at programmed level XXX. (7) G = fade-in to maximum level (RUNFA = 0; VC = 256; RUNFA = 1). (8) H = change in fade time (RUNFA = 0; FT = xxx; RUNFA = 1). (9) I = fade-out to lower volume level and fade time change (RUNFA = 0; new VC; new FT; RUNFA = 1). (10) J = volume regulation stops at programmed level. Note: for illustration only, axes vary in scale.
Fig.11 Volume control example.
7.7.3
DIGITAL SOFT-MUTE
Soft mute is controlled by the microcontroller register file bit MUTE. When the bit is active HIGH the value of the samples is decreased smoothly to zero following a cosine curve. To step down the value of the data 32 coefficients are used, each one being used 32 times before stepping onto the next. This amounts to a mute transition time of 23 ms at fs = 44.1 kHz. When the MUTE bit is LOW, the samples are returned to the full level again following the same cosine curve in reverse order. Mute is synchronized to the sample clock, so that operation always takes place on complete samples. 7.7.4 SCALING AND POLARITY OF THE DIGITAL
UP-SAMPLING FILTER
In the configuration with the default initialization (OUTS0 = 0), the TDA1546T is inverting, meaning that a positive pulse contained in the digital input data is converted to a negative pulse on the analog outputs. This polarity and scaling is identical to that used in TDA1305T. The TDA1546T can be made non-inverting by setting bit OUTS0 in the microcontroller register file. The complete truth table for these bits is shown in Table 10. Table 10 Special control register bits OUTS1 0 0 1 1 OUTS0 0 1 0 1 MODE TDA1305T equivalent non-inverting reserved reserved SCALING -0.9 +0.9 -0.66 -0.99
The scaling factor of the digital up-sampling filter can be selected by means of register file bits OUTS1 and OUTS0. Only those modes controlled by bit OUTS0 are actually useful, the other two are reserved modes and should not be used. January 1995 19
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7.8 7.8.1 Sound processing related features DE-EMPHASIS FILTER 7.8.4 BASS BOOST
TDA1546T
The TDA1546T incorporates selectable digital de-emphasis filters, dimensioned to produce the de-emphasis frequency characteristics for each of the three possible sample rates 32, 44.1 and 48 kHz. With its 18-bit dynamic range, the digital de-emphasis of the TDA1546T is a convenient and component-saving alternative to analog de-emphasis. Selection of the de-emphasis filters is performed via the microcontroller interface, bits DEMC1 and DEMC0. The programming is given in Table 11. Table 11 De-emphasis mode programming DEMC1 0 0 1 1 7.8.2 TREBLE DEMC0 0 1 0 1 DE-EMPHASIS FUNCTION de-emphasis disabled de-emphasis for fs = 32.0 kHz de-emphasis for fs = 44.1 kHz de-emphasis for fs = 48.0 kHz
A strong bass boost effect, which is useful in compensating for poor bass response of portable headphone sets, is implemented digitally in the TDA1546T and can be controlled in 14 steps using the microcontroller bits SCBB3 to SCBB0. Valid settings range from "flat" (no influence on audio) to +37 dB with step sizes varying from 3 dB (lower boosts) to 2.5 dB to 2 dB (higher boosts). The SCBB value 15 is a reserved value and should not be used. (see Table 12). The programmable bass boost filter is a second-order shelving type with a fixed corner frequency of 250 Hz and has a Butterworth characteristic. Because of the exceptional amount of programmable gain, bass boost should be used in conjunction with adequate prior attenuation, using the volume control. The bass stage and the bass boost stage operate independently so that the ultimately attainable gain for low frequencies may reach a total boost of approximately 50 dB. 7.8.5 DIGITAL DYNAMIC BASS BOOST, DIGITAL LOUDNESS
AND OTHER DYNAMIC APPLICATIONS OF TONE CONTROL
A digital treble gain (up to 12 dB in steps of 1.5 dB or cut down to -10.5 dB in steps of 1.5 dB) can be applied to boost or attenuate high-range signal content. The microcontroller bits SCT3 to SCT0 select the treble characteristic to be applied, the effect of which is shown in Table 12. The programmable treble filter is a first-order shelving type with a fixed corner frequency of 2.1 kHz. In the "flat" position the treble stage has no influence on the audio signal path. Because of the possibility of treble boost beyond the available digital headroom causing overload of high frequency range signals, the higher positive treble boost values should generally be used in conjunction with an approximately corresponding attenuation using the volume control function. 7.8.3 BASS
Because of the integration of volume control, tone control and level monitoring functions in the TDA1546T, a wide range of dynamic tone and level control applications is made available. These can be defined in software by the user, thereby replacing and improving on components formerly used to perform these functions in the analog domain. Among these applications the most popular are dynamic bass boost and loudness. Because the volume setting is known in the system controller, it can, for instance, be used directly to determine an appropriate amount of bass boost. This avoids the signal level dependent `sighing', `pumping' and distortion effects typical of analog dynamic bass boost circuits. Depending on the headroom made available by the current volume setting, applying a bass boost of up to 30 dB, combined with a slight treble boost (up to 6 dB) will achieve a typical dynamic bass boost effect of high sound quality. Digital loudness can be realized using the current volume setting to determine a suitable moderate bass gain (up to approximately 15 dB is typical of loudness) and treble gain (up to approximately 6 dB). A further enhancement in dynamic tone control and signal adaptation can be achieved by using the peak monitoring function (either with a flat response or using the band-pass filters) or overload detection (which can also be made frequency-selective) in your dynamic tone control algorithm.
Digital bass control can be applied under control from the microcontroller via control bits SCB3 to SCB0 (see Table 12) to achieve a moderate bass enforcement or attenuation. The programmable bass filter is a first-order shelving type with a fixed corner frequency of 500 Hz. In the "flat" position the bass stage has no influence on the audio signal path. Higher bass settings should generally be compensated by approximately equal attenuation using the volume control to avoid digital overload of basses.
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January 1995 Table 12 Sound processing parameters Philips Semiconductors REGISTER BITS 0000 0001 0011 0010 0101 0100 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 TREBLE SCT3 TO SCT0 (dB) -10.5 10.5 -7.5 -4.5 -1.5 7.5 4.5 1.5 flat 12 -9 -6 -3 9 6 3
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Fig.12 Treble frequency response.
BASS SCB3 TO SCB0 (dB)
21 13.5 10.5 -7.5 -4.5 -1.5 1.5 7.5 4.5 flat -9 -6 -3 9 6 3 12 BASS BOOST SCBB3 TO SCBB0 (dB) Preliminary specification reserved 28.5 23.5 flat 33 12 21 18 15 31 26 3 9 6 35 37
TDA1546T
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January 1995 Philips Semiconductors
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Fig.14 Bass boost frequency response.
Fig.13 Bass frequency response.
22 Preliminary specification
TDA1546T
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January 1995 The sound monitor block consists of a spectrum analyzer, silence detection, peak detection, overload detection and versatile output pins. The position of the sound monitor block can be programmed using microcontroller bit SPOS. When SPOS = 1 the sound monitor block precedes the tone control sections. When SPOS = 0 the sound monitor block succeeds the tone control sections. 7.9 The auxiliary bit LONLY (left only) can be set to enable a special internal channel-copying mode. The left-channel data input is copied internally to the right channel via the The TDA1546T can be used as a two-way digital crossover filter and digital preamplifier in a digital speaker system. In the DSS mode, one TDA1546T is used per loudspeaker channel. The left channel of TDA1546T drives the amplifier for the low frequency transducer and the right channel drives the high-frequency power amplifier. The digital crossover filter is activated by setting the control bit DSS to 1 and the 4-bit bass boost value to its reserved value of 15. Figure 15 shows the frequency transfer function of the digital crossover filter. 7.8.6 Philips Semiconductors Sound monitor block DIGITAL SPEAKER SYSTEM MODE
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Fig.15 Digital crossover filter frequency response.
23 The spectrum analyzer is constructed of a second-order band-pass filter (where the centre frequency is selectable) followed by a resettable peak detector, silence detector and overload detector. The band-pass filter can be set to 7 different frequency bands plus one flat response. The 7 bands are equally spaced in the audio band with a ratio of 1:2.3, which is slightly wider than octave bands. The centre frequencies are given in Table 13. 7.9.1 input data bus and the incoming right channel data is `don't care'. This simplifies interfacing at the input data bus level. Direct connection of the WS line to the TDA1546T appoints the TDA1546T as the left channel processor, and placing an inverter in series with the WS input results in the processing of the right channel data only, thereby appointing the TDA1546T as right channel processor. Consequently, by using LONLY, the normal time-multiplexed I2S-bus or other format can be used rather than a dedicated left or right channel bus. Due to the nature of the digital crossover filter, the digital speaker mode must be used with volume set to -0.375 dB (one unit step below 0 dB) to preclude any occurrence of digital clipping. SPECTRUM ANALYZER Preliminary specification
TDA1546T
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Table 13 Spectrum analyzer frequency band FP2 0 0 0 0 1 1 1 1 FP1 0 0 1 1 0 0 1 1 FP0 0 1 0 1 0 1 0 1 FREQUENCY BAND flat 0 to 99 Hz 189 Hz 435 Hz 1000 Hz 2300 Hz 5290 Hz 12200 Hz SETTLING TIME TO -40 dB OR 1% (ms) - 30 16 5.6 2.4 1.1 0.5 0.2
TDA1546T
frequency bands, e.g. the 189 Hz band takes approximately 16 ms to settle to 1% or -40 dB (i.e. the settling rate is 8 ms per 20 dB). For all bands except the 99 Hz band, the settling rate is inversely proportional to the bandwidth and therefore to the centre frequency. The 99 Hz filter behaves differently because it is, in essence, a first-order low-pass filter. The settling time of the switchable band-pass filter calls for attention to waiting times when used in a spectrum analyzer application. A waiting time is necessary to allow the switching transient to settle. A "dummy" peak readout will then reset the peak detection register to zero, after which instant new frequency-dependent peak data can be accumulated. The time needed to accumulate valid peak information depends on the centre frequency and bandwidth of the band involved, thus a second waiting time will need to be implemented. A peak read action performed after this second waiting time will return an accurate output value.
To scan the whole audio band with one filter, the filter must be switched between the 7 bands. This switching causes a transient which takes time to settle. The settling time is dependent on the bandwidth and is slowest for the low
Fig.16 Spectrum analyzer frequency response.
January 1995
24
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7.9.2 dB CONVERTER
TDA1546T
Before peak data is output, the detected value is converted from linear to a dB scale internally by the TDA1546T. This has the following advantages: * ease calculation load on the system microcontroller * optimal use of dynamic range of the readout * facilitate manipulation of sound processing control levels in combination with peak readout levels, to allow for e.g. dynamic tone control. The internal linear peak detection occurs with a resolution of 16 bits on the incoming left and right audio samples Table 14 Peak readout linear-to-dB conversion (note 1) PEAK DATA 000000 000100 001000 001100 010000 .......... Note PEAK VALUE (dB) - n.a. n.a. n.a. -71.22 ............ PEAK DATA 000001 000101 001001 001101 010001 111101 PEAK VALUE (dB) n.a. n.a. n.a. -76.33 -69.48 -2.87
individually. This linearly acquired value is converted to dB's as shown in Table 14. Because of quantization of the linear code, accuracy is lower for the very lowest detected peak values. Some values in the lower range of the dB scale have no counterpart in the linear scale, consequently these values never occur as output peak words. This is also illustrated in Table 14). The dB conversion block converts only positive linear values to a a useful dB value. All negative input values will be converted to an output value of 3 for recognition.
PEAK DATA 000010 000110 001010 001110 ........... 111110
PEAK VALUE (dB) n.a. n.a. -80.77 -74.75 .......... -1.48
PEAK DATA 000011 000111 001011 001111 ........... 111111
PEAK VALUE (dB) -90.31 -84.29 -78.27 -72.25 ........... 0.00
1. The peak level dB conversion block relates according to the following transfer formula from linear to dB scale: a) Peak value (dB) = (peak data - 63.5) x 5 x log 2 b) The table should be read as follows. The maximum value of 63 (111111) is returned when the detected value resides between -1.48 dB and 0 dB, the next lower value of 62 is returned when the detected value resides between -2.87 dB and -1.48 dB etc. Only true digital silence will return a peak readout value of 000000. c) For peak data > 010011 (= 19) the error in peak level is <(11 x log 2)/4 d) For peak data <010100 (= 20) the error will be larger due to 16 bits accuracy. 7.9.3 PEAK DETECTION the spectrum analyzer, comparing its actual dB value to the value currently stored in the peak register. Any new value greater than the currently held peak value will cause the register to assume the new, greater value. On a peak request (see Section 7.3) the contents of the peak register are transferred to the microcontroller interface. After a read action the peak register will be reset and the collection of new peak data started. The end of a peak read action should be marked by an address mode sequence so that the output peak register is able to latch new data. The peak detection block receives data that has been processed by the de-emphasis block, so if peak data is read when applying digital de-emphasis, the de-emphasis frequency characteristic will be noticeable in the peak output value. 25
The TDA1546T provides a convenient way to monitor the peak value of the audio data, for left and right channels individually, by way of readout via the microcontroller interface. Peak value monitoring has its applications mainly in digital volume unit measurement and display, and in automatic recording level control. The peak level measurement of the TDA1546T occurs with a resolution of 16 bits thus providing a dynamic range amply suitable for all practical applications. The output of the peak detection block is a register of two 6-bit words (one for each channel) which represents the dB linear value of the positive peak value and is accessible via the microcontroller interface. The peak detection block continuously monitors the audio information arriving from January 1995
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
The peak data readout protocol is illustrated in Fig.7. A peak request is performed by activating the address mode of the microcontroller interface (see Table 2). Upon the peak request, the microcontroller will commence collecting data from the internal peak data output register (dB linear, 6-bit left, 6-bit right) on the LOW-to-HIGH transition of L3CLK by sending a clock onto the L3CLK line. The first and last bits of the byte (bit 0 and bit 7 in Fig.7) are padding bits with default set to zero. The first peak bit (bit 1), is the LSB of the channel peak value. The contents of the peak data output register will not change during the peak request. The peak data readout procedure may be aborted at any instant by returning to the address mode, thereby marking the end of the peak request. 7.9.4 SILENCE DETECTION
TDA1546T
Example: silence for 1110 at [ ( 14 + 1 ) x 241 ] x 256 fs = 44.1 kHz = ------------------------------------------------------------( 44100 x 7 ) The TDA1546T itself does not influence the audio signal as a result of digital silence. The sole function of this block is detection, and any further treatment must be accomplished by other means. Silence detected is TRUE when the corresponding channel carries samples smaller than the programmed value for at least the duration of the programmed time. As a separated left/right digital silence detection is not always needed, the logic "AND" function of both left and right digital detection circuits can be logically combined to a mono digital silence indication on pin VERS0, programmed via register control bits PINM1 and PINM0. 7.9.5 OVERLOAD DETECTION
The TDA1546T is designed to detect silence conditions in the left and right channels, separately or combined, and report this via the versatile outputs VERS1 and VERS0 (see Section 7.9.6). The function is programmable in silence level (dB linear via microcontroller register bits SIL3 to SIL0) and silence duration (SILT3 to SILT0) and is implemented to allow external manipulation of the audio signal upon absence of program material, such as muting or recorder control. The silence levels and silence duration timings are given in Table 15. Table 15 Silence detection parameters SILENCE LEVEL SIL3 TO SIL0 0000 0001 0010 .... 1110 1111 SILENCE LEVEL (dB) - -90.3 -87.3 ... -51.2 -48.2 SILENCE DURATION SILT3 TO SILT0 0000 0001 0010 .... 1110 1111 SILENCE DURATION AT 44.1 kHz (s) 0.2 0.4 0.6 ... 3.0 3.2
A level programmable overload detection is present to facilitate applications in digital volume unit measurement and display, and in automatic recording level control. The overload condition of the audio data for left and right channels, individually or combined, is reported via the versatile outputs VERS1 and VERS0 (see Section 7.9.6). The overload levels are given in Table 16. Table 16 Overload detection level OVER3 TO OVER0 0000 0001 .... 1110 1111 DETECTION LEVEL (dB) -46.7 -43.6 ... -4.5 -1.5
The overload detection level from 0000 to 1111 can be obtained using the following equation: Overload if peak level > (2 x OVER - 31) x 5log 2 Overload detected is TRUE when the corresponding channel carries samples greater than the programmed value. A condition of detected overload will be held until peak data is read out from the TDA1546T. This implies that a continuous overload indication (also via the versatile outputs) will function properly only with periodic peak readout taking place. As a separated left/right digital overload detection is not always needed, the logic "OR" function of both left and right digital detection circuits can be logically combined to a mono digital overload indication on pin VERS1, programmed via register control bits PINM1 and PINM0. 26
The silence level and silence duration from 0000 to 1111 can be obtained using the following equations: silence if: sample < (2 x SIL - 62) x 5log 2 Example: silence for 1110: (2 x 14 - 62) x 5log 2 = -51.2 dB [ ( SILT + 1 ) x 241 ] x 256 silence duration = --------------------------------------------------------------------( fs x 7)
January 1995
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
7.9.6 VERSATILE OUTPUTS
TDA1546T
Table 17 Versatile output pin control REGISTER BIT PINM1 0 0 1 1 PVIV1 = 0 PVIV1 = 1 PVIVO = 0 PVIV0 = 1 7.10 Noise shaper PINM0 0 1 0 1 VERS1 mono overload detection left overload detection left digital silence detection no detection OUTPUT MODE VERS0 mono silence detection right overload detection right digital silence detection no detection VERS1 is active HIGH VERS1 is active LOW VERS0 is active HIGH VERS0 is active LOW 7.12 Operational amplifiers
In the normal-speed mode the second-order noise shaper operates at 96fs (fsys = 384fs) or 128fs (fsys = 256fs). In the double-speed mode the noise shaper operates at 48fs (fsys = 384fs) or 64fs (fsys = 256fs). It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique used in combination with a special data coding enables extremely high signal-to-noise ratios to be achieved. The noise shaper outputs a 5-bit PDM bitstream signal to the DAC. 7.11 Continuous calibration digital-to-analog converter
The operational amplifiers and the internal conversion resistors RCONV1 and RCONV2 convert the DAC current to an output voltage which is made available at pins VOL and VOR (typ 1.5 V RMS). Connecting an external capacitor between FILTCL and VOL, FILTCR and VOR respectively provides the required first-order post filtering for the left and right channels. 7.13 Internal reference circuitry
The dual 5-bit DAC uses the continuous calibration technique. This method, based on charge storage, involves exact duplication of a single reference current source. In the TDA1546T, 32 such current sources plus one spare source are continuously calibrated. The spare source is included to allow continuous converter operation. The DAC receives a 5-bit data bitstream from the noise shaper. This data is then converted so that only small currents are switched to the output during digital silence (input 00000H). In this way extremely high-noise performance is achieved.
The Internal reference circuitry ensures that the output voltage signal is proportional to the supply voltage, thereby maintaining maximum dynamic range for supply voltages from 3.8 to 5.5 V. The reference voltage output (pin 26) is intended for external decoupling of the reference voltage. It is a high-impedance output and should not be used to drive external loads, otherwise the performance of the TDA1546T's analog circuitry will be impaired. The voltage at Vref is typically 50% of the analog supply voltage (VDDA).
January 1995
27
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Txtal Tstg Tamb Ves PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 2. Equivalent to discharging a 200 pF capacitor through a 2.5 H inductor. 9 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 75 CONDITIONS - - -65 -20 -3500 -350 MIN.
TDA1546T
MAX. 7.0 +150 +125 +70 +3500 +350 V C C C V V
UNIT
UNIT K/W
10 QUALITY SPECIFICATION In accordance with SNW-FQ-611. The numbers of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9398 510 63011.
January 1995
28
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
11 CHARACTERISTICS Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD VDDA IDDA VDDO IDDO VDDX IDDX RR digital supply voltage digital supply current analog supply voltage analog supply current operational amplifier supply voltage operational amplifier supply current note 1 VDDD = 5 V; at code 00000H note 1 VDDA = 5 V; at code 00000H note 1 VDDO = 5 V; at code 00000H 3.8 - 3.8 - 3.8 - 3.8 - - 5.0 40 5.0 5.5 5.0 6.5 5.0 1 25 5.5 - 5.5 - 5.5 - 5.5 - - PARAMETER CONDITIONS MIN. TYP.
TDA1546T
MAX.
UNIT
V mA V mA V mA V mA dB
clock circuitry supply voltage note 1 clock circuitry supply current VDDX = 5 V; at code 00000H ripple rejection to VDDA crystal frequency system clock duty cycle input leakage current input capacitance note 2
System clock input fxtal Tcy ILI CI Gm Gv VIL VIH VIL VIH ILI CI VIL VIH CI RI fsys = 384fs fsys = 256fs note 3 note 4 9.6 6.4 40 - - - - -0.5 0.8VDD -0.5 0.7VDD - - - 0.7VDD - 17 16.93 11.29 - - - 18.4 12.28 60 10 10 - - MHz MHz % A pF
Master clock mode (see Fig.4) mutual conductance small signal voltage gain fi = 100 kHz Gv = Gm x Go note 5 note 5 6.2 41 - - - - - - - - - - mS V/V
Slave clock mode (see Fig.5) LOW level input voltage HIGH level input voltage 0.2VDD VDD + 0.5 0.3VDD VDD + 0.5 10 10 V V
Digital inputs; WS, BCK, DATA, TEST1, TEST2, L3DATA, L3CLK, L3MODE and CKSL LOW level input voltage HIGH level input voltage input leakage current input capacitance note 5 note 5 note 4 V V A pF
Power-on reset; POR LOW level input voltage HIGH level input voltage input capacitance input resistance note 5 note 5 0.3VDD VDD + 0.5 10 203 V V pF k
January 1995
29
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
SYMBOL PARAMETER CONDITIONS MIN. - - - - 50 - - - 44.1 88.2 - - - - - - - - TYP.
TDA1546T
MAX.
UNIT
Digital outputs; CDEC, VERS0 and VERS1 VOL VOH tr tf MSRCDEC CL fBCK fWS tr tf tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS Notes 1. All VDD and VSS pins must be connected externally to the same supply. 2. Vripple = 1% of the supply voltage; fripple = 100 Hz. 3. Reference levels = 10% and 90%. 4. Minimum ILI measured at Vi = 0 V; maximum ILI measured at Vi = 5.5 V. 5. Minimum VIL and maximum VIH are peak values to allow for transients. 6. Specified duty cycle valid only when used in crystal oscillator applications. LOW level output voltage HIGH level output voltage output rise time output fall time mark-space ratio load capacitance IOL = 4 mA IOH = -4 mA note 3 note 3 output CDEC; note 6 0 VDD - 0.5 - - 45 - - - 25 50 - - 55 55 40 10 40 10 0.5 VDD 20 20 55 30 V V ns ns % pF
Serial input data timing (see Fig.10) bit clock input = data input rate word select input frequency rise time fall time bit clock time HIGH bit clock time LOW data set-up time data hold time word select set-up time word select hold time fsys = 384fs fsys = 256fs normal-speed double-speed 48fs 64fs 48 96 20 20 - - - - - - MHz MHz kHz kHz ns ns ns ns ns ns ns ns
January 1995
30
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
12 ANALOG CHARACTERISTICS VDD = 5 V; VSS = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Reference values Vref RCONV Analog outputs RES tdg VFS(rms) resolution group delay fs = sample rate; normal-speed at 0 dB input level - - 1.425 - 24 ----fs 1.5 reference voltage level current-to-voltage conversion resistor 2.45 1.6 2.5 2.2 PARAMETER CONDITIONS MIN. TYP.
TDA1546T
MAX.
UNIT
2.55 2.8
V k
18 - 1.575
bit s
full-scale output voltage (pins 22 and 25) (RMS value) output voltage DC offset with respect to reference voltage level Vref full-scale temperature coefficient total harmonic distortion plus noise-to-signal ratio
V
VDC(os)
at code 00000H
-80
-65
-50
mV
TCFS (THD+N)/S
- at 0 dB input level; note 1 at -60 dB input level; A-weighted; note 1 at 0 dB input level; (20 Hz to 20 kHz); note 2 - - - - - 100 85 - - 3 -
100 x 10-6 -88 0.004 -44 -85 0.006 108 100 0.2 10 - -
- -81 0.009 -40 -80 0.01 - - 0.3 - - 200 dB % dB dB % dB dB dB k pF
S/N cs |VO| |ZO| ROL COL Notes
signal-to-noise ratio at bipolar zero channel separation imbalance between outputs dynamic output impedance output load resistance output load capacitance
A-weighted; at code 00000H
1. Measured with a 1 kHz sine wave generated at a sampling rate of 48 kHz. 2. Measured with a sine wave swept from 20 Hz to 20 kHz, generated at a sampling rate of 48 kHz.
January 1995
31
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
13 APPLICATION INFORMATION 13.1 Digital filter characteristics (theoretical values)
TDA1546T
Table 18 Normal-speed filter characteristics ITEMS Pass band Stop band SAMPLE FREQUENCY 44.1 kHz 32 kHz 44.1 kHz RANGE 0 to 20 kHz 14.5 to 15 kHz 24.1 to 150 kHz >150 kHz 32 kHz 17 to 17.5 kHz typical worst case typical worst case < -40 dB CHARACTERISTICS 0 0.025 dB > -0.15 dB <-60 dB <-57 dB <-57 dB <-47 dB
Fig.17 Digital filter overall frequency response.
January 1995
32
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January 1995 Philips Semiconductors
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Fig.18 Digital filter pass band ripple.
Fig.19 Digital filter transition band.
33 Preliminary specification
TDA1546T
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
Table 19 Double-speed filter characteristics ITEM Pass band Stop band RANGE 0 to 17 kHz 17 to 20 kHz 24.1 to 150 kHz >150 kHz typical worst case typical worst case Table 20 De-emphasis: deviation from ideal 50 ms to 15 ms characteristic ITEM Gain deviation SAMPLE FREQUENCY 44.1 and 48 kHz 32 kHz Phase deviation 44.1 and 48 kHz 32 kHz RANGE 0 to 18 kHz 18 to 20 kHz 0 to 13 kHz 13 to 15 kHz 0 to 15 kHz 15 to 20 kHz 0 to 9 kHz 9 to 15 kHz 13.2 Example application circuit
TDA1546T
CHARACTERISTICS 0 0.075 dB > -0.3 dB < -47 dB < -45 dB < -33 dB < -25 dB
CHARACTERISTICS 0 0.05 dB <0.12 dB 0 0.06 dB <0.22 dB <10 deg <15 deg <10 deg <16 deg
An example of an application circuit, the schematic for a printed-circuit board available for evaluation, is shown in Fig.20. The following are shown: * the typical connection of the power-on reset pin using a timing capacitor * circuitry surrounding the XTAL1 and XTAL2 pins which can be configured to either crystal oscillator mode (master mode) or external system clock input mode (slave mode) * an example connection for LED indication of digital silence and overload detection (the inverters are optional, used as buffers. The polarity of the versatile output pins programmed via PVIV1 and PVIV0 should reflect the connection polarity of the indicator LEDs) * typical decoupling connection for the Vref pin * typical low component count stereo line output stage (no additional filtering and therefore no external operational amplifiers needed).
January 1995
34
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
TDA1546T
Fig.20 Application diagram (demonstration printed-circuit board).
January 1995
35
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
14 PACKAGE OUTLINE
TDA1546T
handbook, full pagewidth
18.1 17.7
7.6 7.4 A
S 0.9 (4x) 0.4
0.1 S
10.65 10.00
28
15 2.45 2.25 1.1 1.0 0.3 0.1 0.32 0.23 1.1 0.5 detail A 2.65 2.35
pin 1 index 1 14 0 to 8o
MBC236 - 1
1.27
0.49 0.36
0.25 M (28x)
Dimensions in mm.
Fig.21 Plastic small outline package; 28 leads; body width 7.5 mm (SO28; SOT136-1).
January 1995
36
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
15 SOLDERING 15.1 15.1.1 Plastic small-outline packages BY WAVE
TDA1546T
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. 15.1.3 REPAIRING SOLDERED JOINTS (BY HAND-HELD
SOLDERING IRON OR PULSE-HEATED SOLDER TOOL)
During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. 15.1.2 BY SOLDER PASTE REFLOW
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.). For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement
Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
January 1995
37
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
NOTES
TDA1546T
January 1995
38
Philips Semiconductors
Preliminary specification
Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)
NOTES
TDA1546T
January 1995
39
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (081)730-5000, Fax. (081)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD36 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp40 Document order number: Date of release: January 1995 9397 746 30011
Philips Semiconductors

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